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ADT7473
Table 55. TEMPERATURE READING REGISTERS (POWER-ON DEFAULT = 0X01) (Note 1 and 2)
Register Address
0x25
0x26
0x27
R/W
Read-only
Read-only
Read-only
Description
Remote 1 Temperature Reading (8 MSB of Reading) (Note 3 and 4)
Local Temperature Reading (8 MSB of Reading)
Remote 2 Temperature Reading (8 MSB of Reading) (Note 3 and 4)
1. These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration
Register 5 (0x7C).
2. If the extended resolution bits of these readings are also being read, the extended resolution registers (Register 0x76 and Register 0x77)
must be read first. Once the extended resolution registers have been read, all associated MSB reading registers are frozen until read. Both
the extended resolution registers and the MSB registers are frozen.
3. In twos complement mode, a temperature reading of ? 128 ? C (0x80) indicates a diode fault (open or short) on that channel.
4. In Offset 64 mode, a temperature reading of ? 64 ? C (0x00) indicates a diode fault (open or short) on that channel.
Table 56. FAN TACHOMETER READING REGISTERS (POWER-ON DEFAULT = 0X00) (Note 1)
Register Address
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
R/W
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
TACH1 Low Byte
TACH1 High Byte
TACH2 Low Byte
TACH2 High Byte
TACH3 Low Byte
TACH3 High Byte
TACH4 Low Byte
TACH4 High Byte
Description
1. These registers count the number of 11.11 m s periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH
pulses (default = 2). The number of TACH pulses used to count can be changed using the TACH pulses per revolution register (Register 0x7B).
This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two bytes are read, the low byte
must be read first. Both the low and high bytes are then frozen until read. At power-on, these registers contain 0x0000 until the first valid fan
TACH measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF
indicates a fan is one of the following:
? Stalled or blocked (object jamming the fan).
? Failed (internal circuitry destroyed).
? Not populated. (The ADT7473/ADT7473 ? 1 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH
minimum high and low bytes should be set to 0xFFFF.)
? Alternate function, for example, TACH4 reconfigured as THERM pin.
Table 57. CURRENT PWM DUTY CYCLE REGISTERS
(ADT7473 POWER-ON DEFAULT = 0X00, ADT7473 ? 1 POWER-ON DEFAULT = 0XFF) (Note 1)
Register Address
0x30
0x31
0x32
R/W
R/W
R/W
R/W
Description
PWM1 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
PWM2 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
PWM3 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
1. These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the
ADT7473/ADT7473 ? 1 reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature
in automatic fan speed control mode. During fan startup, these registers report back 0x00. In software mode, the PWM duty cycle outputs
can be set to any duty cycle value by writing to these registers.
Table 58. OPERATING POINT REGISTERS (POWER-ON = 0XA4) (Note 1, 2 and 3)
Register Address
0x33
0x34
0x35
R/W (Note 3)
R/W
R/W
R/W
Description
Remote 1 Operating Point Register (Default = 100 ? C)
Local Temperature Operating Point Register (Default = 100 ? C)
Remote 2 Operating Point Register (Default = 100 ? C)
1. These registers set the target operating point for each temperature channel when the dynamic T MIN control feature is enabled.
2. The fans being controlled are adjusted to maintain temperature about an operating point.
3. These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to these registers
fail.
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